Design, implementation and testing of a fully pipelined 5-stage RISC processor following the DLX architecture model

Development of the classic Pac-Man game on a LandTiger Board using C

Emulatation of a custom version of the NXP S32K3X8EVB board with Qemu, integrating UART and CAN peripherals.

A Tcl procedure for PrimeTime that minimizes post-synthesis leakage power